Semiconductor chips are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices. Moreover, it is desirable that the devices operate at very fast speeds.
Among the things that can limit the speed with which semiconductor devices operate is extraneous capacitances in the devices. More specifically, undesired electrical capacitance can arise from the portions of the source and drain regions that overlap the gate region, as well as from the source and drain junctions. To limit junction depth and, hence, to decrease junction capacitance, so-called "silicon on insulator", or "SOI", technology, can be used in which a layer of oxide is buried in the silicon substrate to act as a stop to dopant diffusion (and, hence, to act as a stop to source/drain junction depth).
To isolate adjacent components on a semiconductor device, isolation regions are formed in the substrate between the components. In the context of SOI devices, the isolation regions are formed prior to source/drain dopant implantation by forming trenches down to the buried oxide layer and then filling the trenches with dielectric. As understood by the present invention, however, because the depth at which buried oxide layers are typically formed in a substrate can be as close as 1000 .ANG. to the surface of the substrate to limit junction capacitance, at such a depth the isolation trenches can be insufficiently deep to adequately isolate adjacent device components from each other. With the above shortcomings in mind, the present invention makes the critical observation that it is possible to limit the depth of the source/drain junctions in semiconductor devices (and, hence, decrease the junction capacitances) using shallow buried oxide layers, while nevertheless forming isolation regions between adjacent components that are sufficiently deep to adequately isolate the components from each other.